| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 1 | A Novel Method for Fault Detection using CAM based Approach Authors:BULLINENI VIJITHA, K. REDDAIAH |
01-04 |
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| IJVDCS 2 | A High Performance Gated Voltage Level Translator with Integrated Multiplexer Authors:A. PRAVEEN KUMAR, G. ANUSHA, K. VIJAYA PRASAD |
05-08 |
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| IJVDCS 3 | A Low-Power High-Speed Comparator for Precise Applications Authors:K. DIVYA SREE, S. BHAVANI, K. VIJAYA PRASAD |
09-12 |
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| IJVDCS 4 | Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications Authors:K. AJAY, R. SUNIL, K. VIJAYA PRASAD |
13-15 |
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| IJVDCS 5 | Low-Power and Fast Full Adder By Exploring New XOR and XNOR Gates Authors:P. RAJESH, P. N. SRIKANTH, K. VIJAYA PRASAD |
16-18 |
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| IJVDCS 6 | Design And Implementation of Single Precision Floating Point ALU Authors:HARIOM KUMAR, G. SANKARA RAO |
19-23 |
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| IJVDCS 7 | Implementation of Area and Delay Radix-16 Booth Multiplier for FIR Circuits Authors:P. HEMALATHA, S. EKBAL ALI |
24-27 |
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| IJVDCS 8 | Implementation of Low Complex and Delay in Fault Test Application Time Reduction for Sequential Circuit Authors:K. VAMSI PRIYA SAI, MP. CHENNAIAH |
28-31 |
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| IJVDCS 9 | Realization of Redundant Representation Based SIPO Multiplier For Enhanced Security Applications Authors:C. SREELATHA, S. EKBAL ALI |
32-37 |
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| IJVDCS 10 | Composing A Design And Implementation of Multi Ported Memories On FPGA for Power Efficiency Authors:S. GANESH, M. CHENNAIAH, T. CHAKRAPANI, K. SUDHAKAR |
38-42 |
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